DESA Group: Discrete Event System Analysis

• Study and Development of Verification Methods for Discrete Event Systems

  We are interested on the verification methods of DESs especially based on DEVS formalism. DEVS formalism was prevalently used for simulation but unlike the simulation languages such as SIMULA, SLAM, etc. it has formal semantics. This fact enables us to devise automatic verification methods for DEVS models. When combined with simulation technique our framework could a unified system development environment supporting both the logical analysis and the performance evaluation altogether with the same formalism.

• Performance Measuring of Discrete Event Systems

• Protocol Design and Analysis

• Active Networks

• Rapid prototyping of embedded system, ASIP, DSP, etc.
  -Retargetable simulation / compilation framework 
  -Efficient design space exploration scheme

• Hardware/Software Codesign -HW/SW interface synthesis 
  -Hardware Module Interchange Format

• (Semi-Formal) Verification of H/W

• BDD-based Simulation / Test Generation